8.7. Introduction to make

spot

make can manage the:

• maintenance,
• update,
• regeneration and
• installation

of a set of interconnected files by testing their respective dates of last changes.

It is used in two steps:

1. a file usually named Makefile or makefile describes:

• the dependencies between different files;
• the production rules, or how to update, how to rebuild;

2. after any change in one source file, just type make;

Then make:

• examines the dependencies;
• finds files that are not up-to-date;
• executes the only necessary commands.

8.7.1. Structure of a Makefile:

A configuration file for make may contain essentially three types of lines:

• dependencies
• command lines
• macros

A dependency and the command lines associated is called a rule.

Caution

Do not consider a configuration file Makefile as a program. In particular, there is no “sequential instructions” from beginning to end of the file.

8.7.2. The rules:

They are composed of:

• a rule with dependencies

  this is expressed by a non-empty list of targets to be rebuilt, separated by a space

  • followed by : or ::,
  • followed by the possibly empty list dependencies;

• a production rule

  expressed by a TAB, followed by shell commands to be executed in order to update the target.

Example:

(The characters of a line following a # are ignored by make)

# Prog.exe is generated from object files
prog.exe: prog.o test.o
      cc -o prog.exe prog.o test.o
# ^^^ This should be a TAB
# the previous line is an object files link instruction

In the above example, prog.exe is the target, and its last modification date is compared to those dependencies, prog.o and test.o. The production rule, preceded by a TAB, is the link command cc -o prog.exe prog.o test.o.

It is possible to define rules without dependencies, as rules always executed; example:

# To delete files no longer needed …
clean::
    rm -f *.o core *~

used the following way:

$> make clean

8.7.3. Macros:

• These are lines like: string1 = string2
• They can be defined anywhere in the Makefile
• Any occurrence of $(string1) will be replaced by string2
• The definition of a macro can refer to another macro
• Environment variables are used in the Makefile as macros

There are some predefined widely used macros; most important are:

• dependencies in the rule and production:
  • $? : lists the names of dependent files newer than the target;
  • $@ contains the name of dependent file without its suffix, if any;
• in the production rules only:
  • $* : contains the name of the dependent file without its suffix, if any;
  • $< : contains the filename of the dependency list in process (source file);

8.7.4. An example:

LPR   = lpr -Ppegase
FILES = preface chap1 chap2 chap3 appendix
#
print : $(FILES)
  $(LPR) $?
  touch print
#
printall :
  $(LPR) $(FILES)

8.7.5. Some tips:

• Do not forget the tab (note the confusion with a space) before each production rule. Think about it when you get this message (usual) from make:

  `Make: Must be a separator on rules line #. Stop`

• It should not be any space after the backslash continuation at the end of a line;

  The following command:

  $> cat -t -e Makefile
  

  can display tabs and the end of each line in the configuration file Makefile (with ^I instead of tabs and a $ at the end of each line);

• In some systems, the last line of the makefile must contain a character “new line”;

• Each command line is executed in its own shell:

  cd myTrash
  rm *

  is not the same as:

  cd myTrash; \
  rm *

  equivalent to:

  cd myTrash; rm *

Entry point make in the online manual.